The invention relates to semiconductor power device technology, and more particularly to charge balance field effect transistors and methods of manufacturing same.
The development of device structures for high current switches has seen progress from planar gate vertical DMOS to trench gate structures including those with shield electrodes. Early development projects focused on reducing the specific on-state resistance, RSP. Later, other performance attributes such as gate charge (the charge required to turn the device on and off) were added to the development objectives. More recently, these merit features have evolved into specific unique objectives depending on the specific application for the switch.
Because of its influence on the switching speed of the MOSFET, the product of the specific on-resistance and the gate-drain charge, RSP×QGD, is referred to as the figure-of-merit (FOM) for the top switch in synchronous buck converters which are ubiquitous in many electronic systems. In like fashion, the low side MOSFET whose power dissipation depends on conduction losses, is judged based on a FOM depending on the total gate charge, RSP×QG. Shielded gate structures can significantly improve both of these figures-of-merit. In addition, by increasing the depth of the shield electrode, charge balance can be improved which allows higher than parallel plane breakdown for a given drift region concentration, thus reducing RSP.
Implementing such a charge balance device structure for low voltage MOSFET has proved difficult because of process and material variations resulting in an imbalance in the carrier types which in turn cause reduced breakdown voltage. Assuming charge balance results in a flat electric field in the drift region, it can be shown that the product of the doping concentration N, and the width of the drift region columns W, must be less than the product of the semiconductor permittivity and the critical electric field divided by the electron charge q:
      N    ·    W    <                    ɛ        S            ·              E        C              q  
Consequently, a lower BVDSS target requires greater doping concentration so that the drift region column width must decrease to maintain charge balance. For example, a 30V device with about 2×1016 cm−3 drift region concentration requires a mesa width less that about 1.4 μm for optimum charge balance. This condition however does not result in an improvement in the RSP since 2×1016 cm−3 can support 30V without charge balance. If the concentration is doubled to reduce drift region resistance, the required mesa width is halved to about 0.7 μm. These fine dimensions are difficult to achieve considering all the features that must fit within the cell architecture such as the heavy body junction needed for avalanche ruggedness.
In most charge balance architectures, the drift region is an n-type region on a heavily doped n-type substrate. In some variations, the trench sidewalls are implanted with boron to provide opposite polarity charge. For low voltage devices, each of these methods may suffer from process variations that result in charge imbalance and a relatively wide distribution in the performance features including RSP, QGD, and BVDSS. The process variations come from several sources including epitaxial layer concentration, gate electrode depth relative to the p-well depth, mesa width, and shield dielectric thickness.
Thus there is a need for improved charge balance MOSFET cell structures and methods of manufacture.